1. Field of the Invention
This invention generally relates to signal generators for communication, and more particularly to signal generators for generating a pulse signal having a particular waveform for data transmission. This invention has a particular application to the generation of pulse signals satisfying the pulse mask for interfaces recommended by International Telegraph and Telephone Consultative Committee for Integrated Services Digital Network.
2. Description of the Background Art
Open Systems Interconnection (hereinafter referred to as "OSI") is a network architecture which is now being standardized by International Telegraph and Telephone Consultative Committee (referred to as "CCITT" hereinafter) and International Organization for Standardization (referred to as "ISO" hereinafter) for allowing data transmission between equipments and between systems of computers and terminal devices thereof made by different manufacturers. This standardization is necessary for the implementation of high level data transmission in Integrated Services Digital Network (referred to as "ISDN" hereinafter).
It can be said that ISDN is a system for realizing various communication such as telephone, facsimile communication, data communication, and image communication by a digitalized network. In conventional communication services, the interface between the terminal equipment of the user and the communication network was limited to specific applications, such as for telephone and data communication. In ISDN, an integrated interface is defined for the above-mentioned various services. This interface is called the various purpose user network interface, which is clearly defined by CCITT.
FIG. 6A is a conceptional diagram showing an example of an application of ISDN. Referring to FIG. 6A, ISDN exchange device 400 of the telephone central office and ISDN terminals (TE) of the user's premises 500 are connected via the telephone line in ISDN. User's premises 500 is provided with a network terminating device (NT) 100, to which a telephone line and a four-wire in-house bus are connected. The ISDN terminals are connected to network terminating device 100 via the four-wire in-house bus. The terminating device 100 is provided with an interface circuit 20 for connecting the four-wire in-house bus. Each ISDN device also comprises interface circuit 20.
In addition to the example of the aforementioned ISDN, FIG. 6B shows an example of the primary rate interface in ISDN. This primary rate interface is described in a textbook titled "ISDN Design A Practical Approach" (by S. Hardwick, 1989, ACADEMIC PRESS, Inc. Copywrite). Referring to FIG. 6B, network terminating device 100 is implemented at the entrance of ISDN of the user's site 300 inside the building or factory. Line terminating device 100 is connected to a private branch exchange (PBX) 102 via the four-wire bus. Private branch exchange 102 operates as the user terminal (TE) in ISDN. Terminal equipments 201-20n such as telephones and facsimile machines are connected to private branch exchange 102.
In ISDN, various users terminals are connected to network terminating devices through user-network interfaces. Thus, users are able to receive the services of ISDN via terminals. In Recommendation I. 431 by CCITT, a primary rate user-network interface is defined, with physical and electrical matters concerning the user-network interface described in Layer 1.
FIG. 6C is a conceptional diagram showing the connection between a user terminal TE and a network terminating device NT described in CCITT's Recommendation. As illustrated in FIG. 6C, user-network interfaces Ia and Ib are provided at each I/O port of the user terminal TE and the network terminating device NT, respectively. That is to say, each interface circuit 20 shown in FIGS. 6A and 6B are equivalent to the user network interface 1A or 1B shown in FIG. 6C.
FIG. 6D is a block diagram of the network terminating device 100 shown in FIGS. 6A and 6B. Referring to FIG. 6D, network terminating device 100 comprises a transformer 28 for transmission and reception, a LSI chip 20 for data transmission and reception, and a signal processing circuit 27 of a higher level (Layer 2 for example). The interface circuit 20 shown in FIGS. 6A and 6B is equivalent to LSI chip 20. It is to be noted that LSI chip 20, signal processing circuit 27, and transformer 28 are provided in each user terminal (TE).
In operation, LSI chip 20 transmits transmission data signal 29a and receives reception data signal 29b, via transformer 28. Although transmission data signal 29a has the waveform defined in CCITT's Recommendation which will be explained later, reception data signal 29b has the waveform thereof changed by data transmission. The signal processing circuit 27 provides the data to be transmitted to LSI chip 20, and receives the reception data. The signal processing circuit 27 carries out signal processing in Layer 2 of ISDN.
FIG. 7 is a block diagram showing a circuit configuration of communication LSI chip 20 employed as the user-network interface indicated in FIG. 6C. The LSI chip 20 of FIG. 7 is described in the Preliminary Data Sheet of AT & T titled "LC1046 Digital Signaling Interface". Referring to FIG. 7, LSI chip 20 comprises a receiver 24 and a waveform generator 25 for receiving and transmitting data signals with the user terminal or network terminating device, a timing deriving circuit 21 responsive to a reception signal RX for generating various timing signals, a frame converting circuit 23 for adapting the data frame between higher (Layer 2 for example) signal processing circuits, and an interface circuit 22 for connecting to the signal processing circuit, and a control circuit 26 for controlling the respective circuits in the LSI chip.
In operation, the timing deriving circuit 21 generates various timing signals St in response to data signal RX received by the receiver 24. After the received data signal RX has its data frame converted by the frame converting circuit 23, it is provided to the signal processing circuit via the interface circuit 22. The input signal from the signal processing circuit is applied to the frame converting circuit 23 via the interface circuit 22. Frame converting circuit 23 converts the frame of the data signal which comes from the interface circuit 22, and supplies a converted signal to the waveform generator 25. The waveform generator 25 outputs a pulse signal TX having a predetermined waveform in response to the timing signal from the frame converting circuit 23. The output pulse TX is transmitted towards the user terminal or the network terminating device.
FIG. 8 is a waveform diagram showing the pulse mask (the acceptable range of a pulse waveform) defined by the Recommendation of CCITT. The details of this pulse mask is described in the afore-mentioned textbook titled "ISDN Design A Practical Approach". In FIG. 8, the axis of ordinate indicates the normalized amplitude, and the axis of abscissa indicates the time (ns). The waveform of the pulse signal TX from the waveform generator 25 shown in FIG. 7 is defined within the hatched area of the waveform diagram shown in FIG. 8. One reason why the pulse signal TX requires this particular waveform is that there is a need to prevent the average value of the signal level from having a certain value (i.e. the DC value). That is to say, if pulse signal TX includes a DC signal component, saturation of the pulse transformer utilized in transmission is induced, in addition to the increase in power consumption of the DC current. Moreover, it is required that pulse signal TX has the particular waveform shown in FIG. 8 for also limiting the frequency band of the pulse signal TX.
FIG. 9 is a block diagram showing an example of a waveform generator. Referring to FIG. 9, the waveform generator comprising a memory 3 for storing waveform data to define a pulse signal having a particular waveform, a D/A converter 5 for providing analog signals according to the data from the memory 3, a buffer 10 connected to the output of the D/A converter 5, and a pulse transformer 6 having the primary side connected to the buffer 10 and the constant voltage source 11. From the secondary side of the pulse transformer 6, the pulse signal TX having a determined waveform is provided.
In operation, the memory 3 responds to the clock signal .phi. for applying a waveform data to the D/A converter 5. The D/A converter 5 provides an analog signal according to the applied waveform data, and supplies it to the pulse transformer 6 via the buffer 10. The pulse transformer 6 provides a pulse signal TX according to a difference between the output voltage from the buffer 10 and the voltage output from the constant voltage source 11.
FIG. 10 is a block diagram showing another example of a waveform generator. Referring to FIG. 10, the difference in comparison with the circuit shown in FIG. 9 is that a inverter 13 is connected to the primary side of the pulse transformer 6 in place of the constant voltage source 11. The pulse transformer 6 responds to the complementary voltages output from the buffer 12 and the inverter 13 to generate the pulse signal TX. The waveform generator shown in FIG. 10 can provide a pulse signal TX having an amplitude larger than that of the waveform generator shown in FIG. 9.
Both waveform generators shown in FIGS. 9 and 10 provide the pulse signal TX at the output timing of the D/A converter 5, that is, responds to the sampling pulse .phi.. The D/A converter 5 is formed by a MOS process in the same manner as in the case of the other circuits in the LSI chip. The operating speed of the D/A converter 5 implemented with a MOS transistor is generally lower than that of the one implemented with the bipolar transistor. This means that the frequency of the pulse signal TX provided from the pulse transformer 6 is limited. As a result, it was not possible to obtain a pulse signal TX of a higher frequency when using a conventional waveform generator.
Referring to FIG. 11, the area surrounded by curve 90 is equivalent to the allowable signal waveform of the 1 bit data defined by CCITT's Recommendation. The signal wave form indicated by broken line 91 ideally satisfies the Recommendation. However, the waveform generator shown in FIGS. 9 and 10 generates pulse signal TX of 1 bit data having a signal waveform indicated by curve 92. It is noted that the pulse signal indicated by curve 92 has a low slew rate.
Referring to FIG. 12, the memory 3 shown in FIGS. 9 and 10 provides waveform data DT to D/A converter 5 in response to clock signal .phi.. It can be understood that the waveform generator shown in FIGS. 9 and 10 generates pulse signal TX having the aforementioned low slew rate.